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lt 1122 1 1122fb for more information www.linear.com/lt1122 typical application features description fast settling, jfet input operational amplifier the lt ? 1122 jfet input operational amplifier combines high speed and precision performance. a unique poly-gate jfet process minimizes gate series resistance and gate-to-drain capacitance, facilitating wide bandwidth performance, without degrading jfet transis - tor matching.it slews at 80 v/s and settles in 340 ns. the lt1122 is internally compensated to be unity-gain stable, yet it has a bandwidth of 14 mhz at a supply current of only 7 ma. its speed makes the lt1122 an ideal choice for fast settling 12-bit data conversion and acquisition systems. the lt1122 offset voltage of 120v, and voltage gain of 500,000 also support the 12-bit accurate applications. the input bias current of 10 pa and offset current of 4 pa combined with its speed allow the lt1122 to be used in such applications as high speed sample and hold ampli - fiers, peak detectors, and integrators. 12-bit voltage output d/a converter large-scale response applications n 100% tested settling time 340 ns typ to 1mv at sum node, 10v step 540 ns max tested with fixed feedback capacitor n slew rate 60v/s min n gain-bandwidth product 14mhz n power bandwidth (20v p-p ) 1.2 mhz n unity-gain stable; phase margin 60 n input offset voltage 600v max n input bias current 25c 75 pa max 70c 600pa max input offset current 25c 40 pa max 70 c 150pa max low distortion n fast 12-bit d/a output amplifiers n high speed buffers n fast sample-and-hold amplifiers n high speed integrators n voltage to frequency converters n active filters n log amplifiers n peak detectors l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and c-load is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 0ma to 2ma or 4ma 23 6 c f v0v to 10v out 12-bit current output d/a converterc f = 5pf to 17pf (depending on d/a converter used) + C lt1122 lt1122?ta01 + 200ns/diva v = C1 1122 ta07 5v/div downloaded from: http:///
lt 1122 2 1122fb for more information www.linear.com/lt1122 absolute maximum ratings supply voltage ...................................................... 20 v differential input voltage ....................................... 40 v input voltage .......................................................... 20 v output short circuit duration .......................... indefinite lead temperature ( soldering , 10 sec .) .................. 300 c (note 1) order information operating temperature range lt 1122 am / bm / cm / dm ( obsolete ) .. C55 c to 125 c lt 1122 ac / bc / cc / dc / cs / ds ................. C40 c to 85 c storage temperature range all devices .......................................... C65 c to 150 c 12 3 4 87 6 5 top view Cin+in v C v + outv os trim n8 package 8-lead pdip v os trim speed boost/overcomp t jmax = 150c, ja = 130c/w obsolete package j8 package 8-lead hermetic dip t jmax = 175c, ja = 100c/w 12 3 4 87 6 5 top view v + outv os trim ?in+in v ? s8 package 8-lead plastic so speed boost/overcomp v os trim t jmax = 150c, ja = 190c/w pin configuration lead free finish tape and reel part marking package description temperature range lt1122acn8#pbf lt1122acn8#trpbf lt1122acn8 8-lead plastic dip C40c to 85c lt1122bcn8#pbf lt1122bcn8#trpbf lt1122bcn8 8-lead plastic dip C40c to 85c lt1122ccn8#pbf lt1122ccn8#trpbf lt1122ccn8 8-lead plastic dip C40c to 85c lt1122dcn8#pbf lt1122dcn8#trpbf lt1122dcn8 8-lead plastic dip C40c to 85c lt1122cs8#pbf lt1122cs8#trpbf 1122c 8-lead plastic so C40c to 85c lt1122ds8#pbf lt1122ds8#trpbf 1122d 8-lead plastic so C40c to 85c obsolete package lt1122amj8#pbf lt1122amj8#trpbf lt1122amj8 8-lead hermetic dip C55c to 125c lt1122bmj8#pbf lt1122bmj8#trpbf lt1122bmj8 8-lead hermetic dip C55c to 125c lt1122cmj8#pbf lt1122cmj8#trpbf lt1122cmj8 8-lead hermetic dip C55c to 125c lt1122dmj8#pbf lt1122dmj8#trpbf lt1122dmj8 8-lead hermetic dip C55c to 125c lt1122acj8#pbf lt1122acj8#trpbf lt1122acj8 8-lead hermetic dip C40c to 85c lt1122bcj8#pbf lt1122bcj8#trpbf lt1122bcj8 8-lead hermetic dip C40c to 85c lt1122ccj8#pbf lt1122ccj8#trpbf lt1122ccj8 8-lead hermetic dip C40c to 85c lt1122dcj8#pbf lt1122dcj8#trpbf lt1122dcj8 8-lead hermetic dip C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part markings, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
lt 1122 3 1122fb for more information www.linear.com/lt1122 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v s = 15v, v cm = 0v unless otherwise noted. (note 2) symbol parameter conditions lt1122am/bm lt1122ac/bc lt 1122cm/dm lt1122cc/dc lt1122cs/ds units min ty p max min typ max v os input offset voltage 120 600 130 900 v i os input offset current 4 40 5 50 pa i b input bias current 10 75 12 100 pa input resistance differential common mode v cm = C10v to 8v v cm = 8v to 11v 10 12 10 12 10 11 10 12 10 12 10 11 input capacitance 4 4 pf sr slew rate a v = C 1 60 80 50 75 v/s settling time (note 2) 10v to 0v , C 10 v to 0v 100% tested: a- and c-grades to 1mv at sum node b- and d-grades to 1mv at sum node all grades to 0.5mv at sum node 340 350 450 540 350 360 470 590 ns ns ns gbw gain -bandwidth product power bandwidth v out = 20v p-p 14 1.2 13 1.1 mhz mhz a vol large-signal voltage gain v out = 10v, r l = 2k? v out = 10v, r l = 600? 180 130 500 250 150 110 450 220 v/mv v/mv cmrr common-mode rejection ratio v cm = 10v 83 99 80 98 db input voltage range (note 4) 10.5 11 10.5 11 v psrr power supply rejection ratio v s = 10v to 18v 86 103 82 101 db input noise voltage 0.1hz to 10hz 3.0 3.3 v p-p input noise voltage density f o = 100hz f o = 10khz 25 14 27 15 nv/ hz nv/ hz input noise current density f o = 100hz, f o = 10khz 2 2 fa/ hz v out output voltage swing r l = 2k? r l = 600? 12 11.5 12.5 12 12 11.5 12.5 12 v v i s supply current 7.5 10 7.8 11 ma minimum supply voltage (note 5) 5 5 v offset adjustment range r pot 10k, wiper to v + 4 10 4 10 mv downloaded from: http:///
lt 1122 4 1122fb for more information www.linear.com/lt1122 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at 0c t a 70c. v s = 15v, v cm = 0v. (note 2) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at ?55c t a 125c. v s = 15v, v cm = 0v. (note 2) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at ?40c t a 85c. v s = 15v, v cm = 0v. (note 6) symbol parameter conditions lt1122ac/bc lt1122cc/dc lt1122cs/ds units min typ max min typ max v os input offset voltage l 350 1400 400 2000 v average temperature coefficient of input offset voltage l 5 18 6 25 v/c i os input offset current l 12 150 15 200 pa ib input bias current l 80 600 90 800 pa a vol large-signal voltage gain v out = 10v, r l 2k l 120 380 100 340 v/mv cmrr common-mode rejection ratio v cm = 10v l 82 98 78 96 db psrr power supply rejection ratio v s = 10v to 17v l 84 101 80 99 db input voltage range l 10 10.8 10 10.8 v v out output voltage swing r l = 2k l 11.5 12.4 11.5 12.4 v sr slew rate a v = C1 l 50 70 40 65 v/s symbol parameter conditions lt1122am/bm lt1122cs/ds units min typ max min typ max v os input offset voltage l 650 2400 800 3400 v average temperature coefficient of input offset voltage l 6 18 7 25 v/c i os input offset current l 0.5 6 0.6 9 na i b input bias current l 6 25 7 35 na a vol large-signal voltage gain v out = 10v, r l 2k l 70 230 60 200 v/mv cmrr common-mode rejection ratio v cm = 10v l 80 97 76 94 db psrr power supply rejection ratio v s = 10v to 17v l 83 100 78 98 db input voltage range l 10 10.5 10 10.5 v v out output voltage swing r l = 2k l 11.3 12.1 11.3 12.1 v sr slew rate a v = C1 l 45 60 35 55 v/s symbol parameter conditions lt1122am/bm lt1122cs/ds units min typ max min typ max v os input offset voltage l 450 1900 500 2700 v average temperature coefficient of input offset voltage l 6 20 7 28 v/c i os input offset current l 30 600 40 900 pa i b input bias current l 230 2000 260 2700 pa a vol large-signal voltage gain v out = 10v, r l 2k l 95 340 80 300 v/mv cmrr common-mode rejection ratio v cm = 10v l 80 98 76 96 db psrr power supply rejection ratio v s = 10v to 17v l 83 100 78 98 db input voltage range l 10 10.6 10 10.6 v v out output voltage swing r l = 2k l 11.3 12.2 11.3 12.2 v sr slew rate a v = C1 l 45 60 35 60 v/s downloaded from: http:///
lt 1122 5 1122fb for more information www.linear.com/lt1122 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt1122 is measured in an automated tester in less than one second after application of power. depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed up chip temperature can be 10c to 50c higher than the ambient temperature. note 3: settling time is 100% tested for a- and c-grades using the settling time test circuit shown. this test is not included in quality assurance sample testing. note 4: input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 4mv (a, b grades), to 5.7mv (c, d grades).note 5: minimum supply voltage is tested by measuring offset voltage to 7mv maximum at 5v supplies.note 6: the lt 1122 is not tested and not quality-assurance-sampled at C40c and at 85c. these specifications are guaranteed by design, correlation and/or inference from C55c, 0c, 25c, 70c and/or 125c tests. 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 15v 1f tant 0.1f 1f tant 0.1f typical supply bypassing for each amp/buffer C10v (regulated) 1 2 ttl in 4 5 74ls00 ground all other inputs 10v (regulated) 6 3 settling time output (20 times sum node output) 1k no connection on pins 10, 11, 12, 14, and 15 1n5712 15v C15v 1.5k lt1223 C + 32 4 7 6 8 1 7 2 5 4 1n5712 summingnode output C15v 15v *this resistor can be adjusted to null out all offsets at the settling time output. the automated tester uses a separate autozero circuit. C15v (measure input pulse here) v in 5.1k 1% 4 C15v 3 2 7 6 lt1122 2k 1% 15v 2k 1% device under test 5pf 15v 7 1 5 2 8 51 51 51 51 + C ha5002 79 5.1k* 1% ha5002 4 ltc201a lt1122?ta02 C15v + + settling time test fixture downloaded from: http:///
lt 1122 6 1122fb for more information www.linear.com/lt1122 typical performance characteristics settling time (input from 0v to ?10v) large-signal response undistorted output swing vs frequency voltage gain vs frequency gain, phase vs frequency common-mode rejection vs frequency settling time (input from ?10v to 0v) settling time (input from 10v to 0v) settling time (input from 0v to 10v) 100ns/div 1122 g01 1mv/div at sum node 100ns/div 1122 g02 1mv/div at sum node 100ns/div 1122 g03 1mv/div at sum node 100ns/div 1122 g04 1mv/div at sum node 200ns/div a v = 1 1122 g05 5v/div frequency (hz) 100k 0 peak-to-peak output swing (v) 10 20 25 30 1m 10m 100m v = 15vt = 25c 15 5 s a 1122 tpc01 frequency (hz) 1 0 gain (db) 20 40 60 80 100 120 10 100 1k 10k C20C40 100k 1m 10m 100m v = 15vt = 25c s a 1122 tpc02 frequency (hz) 1m 10 gain (db) 10 20 100m 10m 0 80100 120 140 160 180 200 v = 15vt = 25c c = 15pf s a l phase shift (degrees) 1122 tpc03 frequency (hz) 100 0 common-mode rejection ratio (db) 20 40 60 80 100 120 1k 10k 1m 100m v = 15vt = 25c s a 100k 10m 1122 tpc04 downloaded from: http:///
lt 1122 7 1122fb for more information www.linear.com/lt1122 typical performance characteristics warm-up drift noise spectrum 0.1hz to 10hz noise total harmonic distortion + noise vs frequency inverting gain total harmonic distortion + noise vs frequency noninverting gain intermodulation distortion (ccif method) vs frequency lt1122 and lf156* distribution of input offset voltage input bias and offset currents over temperature bias and offset currents over the common-mode range input offset voltage (v) C900 0 number of units 200 400 600 800 C500 C100 100 500 v = 15vt = 25c (not warmed up) s a 3370 units testedin all packages 1122 tpc05 900 chip temperature (c) 0 1 input bias and offset currents (pa) 300 1k 3k 10k 25 50 75 100 125 100 30 10 3 bias current offsetcurrent v = 15vv = 0v s cm 1122 tpc06 30k 100k common-mode input voltage (v) 15 0 input bias and offset current (pa) 20 40 60 80 100 120 10 5 5 15 v = 15vt = 25c s a 0 10 (not-warmed up) bias current offset current 1122 tpc07 time after power on (minutes) 0 1 change in offset voltage (v) 50 100 150 200 250 1 2 3 v = 15vt = 25c s a j package n package so package in still air (so package soldered onto board) 1122 tpc08 frequency (hz) 1 10 voltage noise density (nv / hz ) 100 1000 3 10 10k 30 100 300 1k 3k v = 15vt = 25c s a 1122 tpc09 time (seconds) 0 noise voltage (1v/div) 2 4 8 10 6 1122 tpc10 frequency (hz) 20 0.0001 total harmonic distortion + noise (%) 0.001 0.01 0.1 100 1k 20k a v = C50 a v = C10 a v = C1 10k t = 25cv = 15v z = 5k//15pf v = 7v rms as l o 1122 tpc11 frequency (hz) 20 0.0001 total harmonic distortion + noise (%) 0.001 0.01 0.1 100 1k 20k a v = 50 a v = 10 a v =1 10k t = 25cv = 15v z = 5k//15pf v = 7v rms as l o 1122 tpc12 frequency (hz) 3k 0.0001 intermodulation distortion (imd) (%) 0.001 0.01 0.1 10k 20k lt1122 lf156 v = 15vt = 25c a = C10 v = 7v rms z = 5k//15pf sa v o l *see lt1115 data sheet for definition of ccif testing 1122 tpc13 downloaded from: http:///
lt 1122 8 1122fb for more information www.linear.com/lt1122 applications information settling time measurements settling time test circuits shown on some competitive devices data sheets require: 1. a flat top pulse generator. unfortunately, flat top pulse generators are not commercially available. 2. a variable feedback capacitor around the device under test. this capacitor varies over a four-to-one range. presumably, as each op amp is measured for settling time, the capacitor is fine tuned to optimize settling time for that particular device. 3. a small inductor load to optimize settling. the lt1122 s settling time is 100% tested in the test circuit shown. no flat top pulse generator is required. the test circuit can be readily constructed, using commercially available ics. of course, standard high frequency board construction techniques should be followed. all lt1122s are measured with a constant feedback capacitor. no fine tuning is required. speed boost/overcompensation terminal pin 8 of the lt1122 can be used to change the input stage operating current of the device. shorting pin 8 to the posi - tive supply ( pin 7) increases slew rate and bandwidth by about 25%, but at the expense of a reduction in phase margin by approximately 18 degrees. unity - gain capacitive load handling decreases from typically 500pf to 100pf. conversely, connecting a 15 k resistor from pin 8 to ground pulls 1 ma out of pin 8 ( with v + = 15 v). this reduces slew rate and bandwidth by 25%. phase margin and capacitive load handling improve; the latter typically increasing to 800pf.high speed operation as with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. the power supply connections to the lt1122 must maintain a low impedance to ground over a bandwidth of 20 mhz. this is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. multiple high quality bypass capacitors are recommended for each power supply line in any critical application. a 0.1 f ceramic and a 1 f electrolytic capacitor, as shown, placed as close as possible to the amplifier ( with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. v + 7 2 6 3 4 1f 0.1f 1f 0.1f v C lt1122 1122 ta03 + C + + when the feedback around the op amp is resistive ( r f ), a pole will be created with r f , the source resistance and capacitance ( r s , c s ), and the amplifier input capacitance (c in 4 pf). in low closed-loop gain configurations and with r s and r f in the kilohm range, this pole can create excess phase shift and even oscillation. a small capaci- tor ( c f ) in parallel with r f eliminates this problem. with r s ( c s + c in ) = r f c f , the effect of the feedback pole is completely removed. r s c s c in r f c f output + C 1122 ta04 downloaded from: http:///
lt 1122 9 1122fb for more information www.linear.com/lt1122 typical applications quartz stabilized oscillator with 9ppm distortion w distortiontrim 50k 430pf 560k 47k 4khzj cut lt1010 lt1122 + C lt1122 C15v 15v 2k 1/4 ltc201 ground crystal case = vactec vtl5c10 or clairex clm410 = 1n4148 15v 1m 560k100k q1 2n3904 15v 1122 ta05 C+ 4.7k 4.7k 5k outputamplitude trim 10f 470 lt1006 lt10042.5v 4.7k C15v output + C mount in close proximity + downloaded from: http:///
lt 1122 10 1122fb for more information www.linear.com/lt1122 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. n8 rev i 0711 .065 (1.651) typ .045 C .065 (1.143 C 1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min .008 C .015 (0.203 C 0.381) .300 C .325 (7.620 C 8.255) .325 +.035C.015 +0.889C0.381 8.255 ( ) 1 2 3 4 8 7 6 5 .255 .015* (6.477 0.381) .400* (10.160) max note:1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510 rev i) downloaded from: http:///
lt 1122 11 1122fb for more information www.linear.com/lt1122 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. j8 0801 .014 C .026 (0.360 C 0.660) .200 (5.080) max .015 C .060 (0.381 C 1.524) .125 3.175 min .100 (2.54) bsc .300 bsc (7.62 bsc) .008 C .018 (0.203 C 0.457) 0 C 15 .005 (0.127) min .405 (10.287) max .220 C .310 (5.588 C 7.874) 1 2 3 4 8 7 6 5 .025 (0.635) rad typ .045 C .068 (1.143 C 1.650) full lead option .023 C .045 (0.584 C 1.143) half lead option corner leads option (4 plcs) .045 C .065 (1.143 C 1.651) note: lead dimensions apply to solder dip/plate or tin plate leads j8 package 3-lead cerdip (narrow .300 inch, hermetic) (reference ltc dwg # 05-08-1110) obsolete package downloaded from: http:///
lt 1122 12 1122fb for more information www.linear.com/lt1122 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 rev g 0212 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note:1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 4. pin 1 can be bevel edge or a dimple s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) downloaded from: http:///
lt 1122 13 1122fb for more information www.linear.com/lt1122 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. rev date description page number b 02/14 updated data sheet to current standards. new order information table, package descriptions 2, 10-12 revision history (revision history begins at rev b) downloaded from: http:///
lt 1122 14 1122fb for more information www.linear.com/lt1122 ? linear technology corporation 1991 lt 0214 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt1122 related parts typical application part number description comments lt1022 high speed precision jfet op amp 23v/s min slew rate, 250v v os lt1055/lt1056 precision high speed jfet op amps 16v/s slew rate, 150v v os lt1464 1mhz c-load? stable jfet op amp capacitive loads up to 10nf lt c ? 6244 50mhz low noise cmos op amp 1pa i b , 100v max v os , 1.5v p-p , 0.1hz to 10hz noise wide-band, filtered, full wave rectifier in v out e dc + C 1f 200k 1% 20k 1% 100k 1% 1k 50k 200k 1% 20k 1% lt1122 output dc = rms value of inputbandwidth with 10v p-p input = 2mhz + C lt1122 1122 ta06 downloaded from: http:///

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